Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer

doi:10.1007/s40195-019-00948-6

Abstract

Abstract:

Cu pillar bump offers a number of advantages for flip chip packaging, compared to the conventional solder bump. However, due to its rigidity structure, Cu pillar bump introduces a lot of stress to the chip, which causes the failure of packaging structures, especially for the advanced node devices which typically have brittle low K dielectric material. In this paper, for the first time we propose two types of Cu pillar structures to reduce the stress. The first Cu pillar structure has bigger Cu dimensions at the base. The other one is designed to add an additional Cu pad under the Cu pillar bump. Finite element analysis is used to study the stress of the both structures, and it is found that with the increase in pillar bump contact area over the chip surface, the stress decreases in both structures. Results also indicate that the Cu pillar bump undercut induces higher stress, and thin Cu₆Sn₅ intermetallic compound has less impact on the stress during flip chip mount reflow. The study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.

Key words: Cu pillar bump, Flip chip, Low K stress, Undercut

Xin-Jiang Long, Jin-Tang Shang, Li Zhang. Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer[J]. Acta Metallurgica Sinica (English Letters), 2020, 33(4): 583-594.

Figures/Tables 16

Fig. 1 Failure image of low K material layer showing delamination and crack beneath Cu pillars

Fig. 2 Two kinds of Cu pillar bump structures and undercut: a standard Cu pillar bump, b Cu pillar bump with Cu pad, c undercut of bump, d Cu pillar bump with IMC

Table 1 Cu pillar bump key dimension (Unit: μm)

Fig. 3 Illustration of the modeling: a the sketch of entire package, b bump layout, c global view of model of 1/2 of one strip in the diagonal of the package, d, e local model of bump area, f side view of local model of bump area, g layer identification

Fig. 4 Reflow profile of the Cu pillar bump

Table 2 Material properties and layer thickness

Table 3 Material parameters of ANAND model for Sn

Fig. 5 Simulated stress distribution: a stress contour of in plane, b zoom in for stress contour of in plane, c stress contour of out plane, d zoom in for stress contour of out plane

Table 4 Maximum stress in low K layer and out of low K layer versus Cu pillar bump structure

Fig. 6 Interfacial stresses of group A structure: a in-plane stress, b out-plane stress

Fig. 7 Interfacial stresses of group B structure compared to A-2 structure: a in-plane stress, b out-plane stress

Table 5 Cu pillar bump key dimension for design optimization application and experiment result (Unit: μm)

Fig. 8 Optical picture of mechanical failure in chip

Fig. 9 Interfacial stresses of group C structure compared to A-2 structure: a in-plane stress, b out-plane stress

Fig. 10 Interfacial stresses of group D structure compared to A-2 structure: a in-plane stress, b out-plane stress

Table 6 Variance analysis for structure factors

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